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HT86Axx/HT86ARxx A/D Type Voice 8-Bit MCU
Technical Document
* Application Note - HA0075E MCU Reset and Oscillator Circuits Application Note
Features
* HT86AXX Operating voltage: 2.0V~5.5V * Four 8-bit programmable Timer with overflow
HT86ARXX Operating voltage: 2.2V~5.5V
* System clock: 4MHz~8MHz * Crystal and RC system oscillator * 40 I/O pins * 8K16-bit Program Memory * 3848-bit Data Memory * 768/1536K-bit voice ROM size * 36/72 sec voice length * External interrupt input * 12-bit high quality voltage type D/A output * 4 channels 12-bit resolution A/D Converter * SPI series protocol interface * Integrated 1W power amplifier to drive 8W Speaker
interrupt and 7-stage prescaler
* One optional 32768Hz crystal oscillator for RTC
time base
* 8-bit counter with 3-bit prescaler * Watchdog timer function * 8-level subroutine nesting * Low voltage reset and low voltage detect function * Integrated voice ROM with various capacities * Power-down function and wake-up feature reduce
power consumption
* Up to 0.5ms instruction cycle with 8MHz system
clock at VDD= 5V
* 63 powerful instructions * 44-pin QFP and 64-pin LQFP packages
General Description
The devices are Voice type series 8-bit high performance microcontrollers which include a voice synthesiser and tone generator. They are specifically designed for applications which require multiple I/Os and sound effects, such as voice and melodies. They can provide various sampling rates and beats, tone levels, tempos for speech synthesisers and melody generators. They also include an integrated high quality, voltage type DAC output, an integrated series protocol interface, multi-channel A/D Converter and integrated power amplifier for speaker driving. The external interrupt can be triggered with falling edges or both falling and rising edges. The devices are fully supported by the Holtek range of fully functional development and programming tools, providing a means for fast and efficient product development cycles.
Rev. 1.00
1
March 19, 2010
HT86Axx/HT86ARxx
Selection Table
The devices include a comprehensive range of features, with most features common to all devices. The main features distinguishing them are Voice ROM capacity and power supply voltage. The functional differences between the devices are shown in the following table. Devices which include an A in their part number are Mask type while devices which contain an R in their part number are OTP type. Program Data Memory Memory Voice ROM 968 8K16 3848 1928 72sec Voice Capacity 36sec 40 8-bit4 12-bit1 8 44QFP, 64LQFP Package Types
Part No. HT86A36 HT86A72
VDD 2.0V~ 5.5V
I/O
Timer
D/A
Stack
2.2V~ HT86AR72 5.5V
Note: Voice length is estimated by 21K-bit data rate
Block Diagram
W a tc h d o g T im e r S ta c k 8 - b it R IS C MCU C o re Low V o lta g e D e te c t Low V o lta g e R eset
W a tc h d o g T im e r O s c illa to r R eset C ir c u it In te rru p t C o n tr o lle r R C /C ry s ta l O s c illa to r
P ro g ra m M e m o ry
V o ic e ROM
R A M D a ta M e m o ry
A /D C o n v e rte r I/O P o rts RTC 8 - b it T im e r D /A C o n v e rte rs S e r ia l In te rfa c e Power A m p lifie r
Rev. 1.00
2
March 19, 2010
HT86Axx/HT86ARxx
Pin Assignment
RES PD6 PD5 PD4 PA7 PA6 PA5 PA4 PA3 PA2 PA1 1 0 3 2 2 3 1 4 0 5 0 6 1 7 2 8 3 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 RES PD6 PD5 PD4 PA7 PA6 PA5 PA4 PA3 PA2 PA1 44 43 42 41 1 0 3 2 2 3 1 4 0 5 0 6 1 7 2 8 3 9 10 11 12 13 14 15 16 17 18 19 20 21 22 HT86A 72 HT86A R72 4 4 Q F P -A 40 39 38 37 36 35 34
PA PC PC PC PC PD PD PD PD
33 32 31 30 29 28 27 26 25 24 23
HT86A 36 4 4 Q F P -A
VDDA1 VSSA1
X IN XO VD PE PE VS IN T PE OS OS PC 4 5 S 6
UT D
C2 C1 5
PA PC PC PC PC PD PD PD PD
33 32 31 30 29 28 27 26 25 24 23
VDDA1 VSSA1
X IN XO VD PE PE VS IN T PE OS OS PC 4 5 S 6
UT D
C2 C1 5
PA0 NC NC PA1 PA2 PA3 PA4 PA5 PA7 PC3 PC2 PC1 PC0 PD0 PD1 PD2 1 2 3 4 5 6 7 8 9
64636261605958575655545352515049
SPVSS VDD VSS SP+ V B IA AUD AUD VDD VSS VRE A F A S _ IN _O U T PE2 PE1 PE0 PD7 PD6 PD5 PD4 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA6 10 11 12 13 14 15 16 1718192021 2223242526272829303132 H T86A 36 6 4 L Q F P -A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PE3 RES X IN XOUT VDD PE4 PE5 VSS IN T PE6 OSC2 OSC1 PE7 PC7 PC6 PC5 PA N N PA PA PA PA PA PA PC PC PC PC PD PD PD C C 1 2 3 4 5 7 3 2 1 0 0 1 2 9 8 10 11 12 13 14 15 7 6 5 4 0 1 2 3 SPVSS VDD VDD VSS SP+ V B IA AUD AUD VDD VSS PC4 VRE VDD VSS PD3 F A1 A1 A A S _ IN _O U T M M M M M M M
64636261605958575655545352515049
16 1718 192021 2223242526272829303132
SPVSS VDD VSS SP+ V B IA AUD AUD VDD VSS VRE A F A PE2 PE1 PE0 PD7 PD6 PD5 PD4 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA6 H T86A 72 H T86A R 72 6 4 L Q F P -A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PE3 RES X IN XOUT VDD PE4 PE5 VSS IN T PE6 OSC2 OSC1 PE7 PC7 PC6 PC5 SPVSS VDD VDD VSS SP+ V B IA AUD AUD VDD VSS PC4 VRE VDD VSS PD3 F A1 A1 A A S _ IN _O U T M M M M S _ IN _O U T M M M
Rev. 1.00
3
March 19, 2010
HT86Axx/HT86ARxx
Pad Assignment
HT86A36
1
67 66
65
64
63 62
61 60
59 58
57
56
55 54
53
52
51 50
49
48
47
46 44 43 42
45
41
(0 ,0 )
40 39 38 37 36
2 3 4 5 6 7 8 9 10 11 12 13 1415161718 19 20 21 22 23 24 25 26 27 28 29
35 34
33 32 31 30
Chip Size: 2655 2725 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.00
4
March 19, 2010
HT86Axx/HT86ARxx
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pad Name PA0 PC3 PC2 PC1 PC0 PD0 PD1 PD2 PD3 VSSA1 VDDA1 VREF PC4 NC NC NC NC NC VSSA VDDA AUD_OUT AUD_IN VBIAS SP+ VSSM VDDM VDDM VSSM SPPC5 PC6 PC7 PE7 OSC1 X -1141.487 -1177.862 -1177.862 -1177.862 -1177.862 -1150.059 -1150.059 -1150.059 -1150.059 -1215.319 -1008.914 -906.508 -803.508 -672.868 -596.868 -520.868 -444.868 -368.868 -220.317 -113.217 8.383 156.311 289.311 391.136 498.085 605.036 733.086 840.037 946.986 1174.567 1174.567 1174.567 1174.567 1175.250 Y 1211.389 -380.061 -483.061 -578.061 -681.061 -789.182 -892.182 -987.182 -1090.182 -1257.457 -1225.000 -1213.900 -1213.900 -1082.529 -1082.529 -1082.529 -1082.529 -1082.529 -1116.909 -1121.909 -1151.309 -1146.077 -1146.077 -1101.247 -1101.247 -1101.247 -1101.247 -1101.247 -1101.247 -1158.350 -1055.350 -960.350 -857.350 -499.731 Pad No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Pad Name OSC2 PE6 INT VSS PE5 PE4 VDD XOUT XIN RES PE3 PE2 PE1 PE0 PD7 PD6 PD5 PD4 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 X 1175.250 1175.250 1175.250 1174.567 1174.567 1174.567 1174.567 1174.450 1174.450 1174.450 1166.013 1063.013 941.513 838.513 743.513 640.513 545.513 442.513 347.513 244.513 149.513 46.513 -48.487 -151.487 -246.487 -349.487 -444.487 -547.487 -642.487 -745.487 -840.487 -943.487 -1038.487 Unit: mm Y -400.731 -296.331 -201.331 -90.426 19.807 122.807 226.177 794.097 897.097 992.097 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389 1211.389
Rev. 1.00
5
March 19, 2010
HT86Axx/HT86ARxx
HT86A72
1
67 66
65
64
63 62
61 60
59 58
57 56
55
54
53 52
51 50
49
48
47
46 44 43 42
45
41 40
(0 ,0 )
39 38 37 36
2 3 4 5 6 7 8 9 10 11 12 13 1415161718 19 20 21 22 23 24 25 26 27 28 29 35 34 33 32 31 30
Chip Size: 2651 3078 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.00
6
March 19, 2010
HT86Axx/HT86ARxx
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pad Name PA0 PC3 PC2 PC1 PC0 PD0 PD1 PD2 PD3 VSSA1 VDDA1 VREF PC4 NC NC NC NC NC VSSA VDDA AUD_OUT AUD_IN VBIAS SP+ VSSM VDDM VDDM VSSM SPPC5 PC6 PC7 PE7 OSC1 X -1139.487 -1175.862 -1175.862 -1175.862 -1175.862 -1148.059 -1148.059 -1148.059 -1148.059 -1213.319 -1009.034 -906.613 -803.613 -671.507 -595.507 -519.507 -443.507 -367.507 -218.317 -111.217 10.383 158.311 261.311 393.136 500.085 607.036 735.086 842.037 948.986 1176.567 1176.567 1176.567 1176.567 1177.250 Y 1389.643 -556.476 -659.476 -754.476 -857.476 -965.628 1068.682 -1163.682 -1266.682 -1433.997 -1401.500 -1390.400 -1390.400 -1258.234 -1258.234 -1258.234 -1258.234 -1258.234 -1293.409 -1298.409 -1327.809 -1322.577 -1322.577 -1277.747 -1277.747 -1277.747 -1277.747 -1277.747 -1277.747 -1334.850 -1231.850 -1136.850 -1033.850 -916.231 Pad No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Pad Name OSC2 PE6 INT VSS PE5 PE4 VDD XOUT XIN RES PE3 PE2 PE1 PE0 PD7 PD6 PD5 PD4 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 X 1177.250 1177.250 1177.250 1176.567 1176.567 1176.567 1176.567 1176.450 1176.450 1176.450 1141.513 1038.513 943.513 840.513 745.513 642.513 547.513 444.513 349.513 246.513 151.513 48.513 -46.487 -149.487 -244.487 -347.487 -442.487 -545.487 -640.487 -743.487 -838.487 -941.487 -1036.487 Unit: mm Y -817.231 -232.827 -137.827 -27.172 82.881 185.881 289.431 892.351 995.351 1090.351 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643 1389.643
Rev. 1.00
7
March 19, 2010
HT86Axx/HT86ARxx
HT86AR72
1
67 66
65 64 63
62
61 60 59
58
57
56
55 54
53 52
51 50
49 48
47 46
45
(0 ,0 )
44 43 42 41 40 39 38 37 36
2 3 4 5 6 7 8 9 10 11 12 13 14 1516 1718 19 20 21 22 23 24 25 26 27 28 29 35 34 33 32 31 30
Chip Size: 2580 5870 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.00
8
March 19, 2010
HT86Axx/HT86ARxx
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pad Name PA0 PC3 PC2 PC1 PC0 PD0 PD1 PD2 PD3 VSSA1 VDDA1 VREF PC4 NC NC NC NC NC VSSA VDDA AUD_OUT AUD_IN VBIAS SP+ VSSM VDDM VDDM VSSM SPPC5 PC6 PC7 PE7 OSC1 X -1138.054 -1138.629 -1138.629 -1138.629 -1138.629 -1110.826 -1110.826 -1110.826 -1110.826 -1176.086 -968.465 -873.465 -770.465 -638.243 -562.243 -486.243 -410.243 -334.243 -232.480 -131.115 -28.525 120.644 223.644 355.469 462.418 569.369 697.419 804.370 911.319 1138.900 1138.900 1138.900 1138.900 1138.900 Y 2785.633 -1952.576 -2055.576 -2150.576 -2253.576 -2361.132 -2464.132 -2559.132 -2662.132 -2827.757 -2785.850 -2785.850 -2785.850 -2804.019 -2804.019 -2804.019 -2804.019 -2804.019 -2738.114 -2739.664 -2739.664 -2718.027 -2718.027 -2673.197 -2673.197 -2673.197 -2673.197 -2673.197 -2673.197 -2696.357 -2593.357 -2498.357 -2395.357 -2274.826 Pad No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Pad Name OSC2 PE6 INT VSS PE5 PE4 VDD XOUT XIN RES PE3 PE2 PE1 PE0 PD7 PD6 PD5 PD4 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 X 1138.850 1138.668 1138.668 1138.985 1138.985 1138.985 1138.900 1138.908 1138.908 1138.906 1142.946 1039.946 944.946 841.946 746.946 643.946 548.946 445.946 350.946 247.946 152.946 49.946 -45.054 -148.054 -243.054 -346.054 -441.054 -544.054 -639.054 -742.054 -837.054 -940.054 -1035.054 Unit: mm Y -2171.224 -1669.854 -1574.854 -1432.154 -1321.921 -1218.921 -1110.526 -994.167 -891.167 -761.007 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633 2785.633
Rev. 1.00
9
March 19, 2010
HT86Axx/HT86ARxx
Pin Description
Pin Name I/O Options Wake-up, Pull-high Description Bidirectional 8-bit I/O port. Each pin on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have a pull-high resistor. Bidirectional 8-bit I/O port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have a pull-high resistor. Bidirectional 8-bit I/O port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have a pull-high resistor. Pins PC0~PC3 are pin-shared with A/D converter input pins AD0~AD3. Bidirectional 8-bit I/O port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pin on the port have a pull-high resistor. Pins PD0~PD3 are pin-shared with SPI interface pins SCS, SCK, SDI, SDO. Bidirectional 8-bit I/O port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have a pull-high resistor. Audio output for driving an external transistor or for driving HT82V739 Power amplifier input pin Power amplifier output pins Voltage bias pin Schmitt trigger reset input. Active low.
PA0~PA7
I/O
PB0~PB7 PC0/AD0 PC1/AD1 PC2/AD2 PC3/AD3 PC4~PC7 PD0/SCS PD1/SCK PD2/SDI PD3/SDO PD4~PD7 PE0~PE7 AUD_OUT AUD_IN SP-, SP+ VBIAS RES
I/O
Pull-high
I/O
Pull-high
I/O
Pull-high
I/O O I
Pull-high 3/4 3/4 3/4 3/4 3/4
O I
INT
I
Falling Edge External interrupt Schmitt trigger input without pull-high resistor. A configuration Trigger or option determines if the interrupt active edge is a falling edge only or both a falling Falling/Rising and rising edge. Edge Trigger Crystal or RC OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency. Connected to an external 32kHz crystal A/D circuit reference voltage Positive digital power supply Negative digital power supply, ground. Positive DAC circuit power supply Negative DAC circuit power supply, ground Positive A/D circuit power supply Negative A/D circuit power supply, ground Positive Power Amp. power supply Negative Power Amp. power supply, ground
OSC1 OSC2 XIN XOUT VREF VDD VSS VDDA VSSA VDDA1 VSSA1 VDDM VSSM
3/4
3/4 I 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Crystal 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Individual pins can be selected to have pull-high resistors.
Rev. 1.00
10
March 19, 2010
HT86Axx/HT86ARxx
Absolute Maximum Ratings
Supply Voltage ...........................VSS+2.0V to VSS+5.5V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Test Conditions Symbol VDD VDD Parameter VDD HT86AXX Operating Voltage HT86ARXX Operating Voltage Conditions 2.0 2.2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 5.5 5.5 1.5 5.0 3.0 7.0 10 18 20 36 1.5 5.0 3.0 7.0 10 18 20 36 5 10 2 4 4 8 1.0 2.0 0.3VDD VDD 3/4 fSYS=4MHz/8MHz 3/4 fSYS=4MHz/8MHz 3V No load, f SYS=4MHz, 5V RTC enable, DAC disable Operating Current 3V No load, f SYS=8MHz, 5V RTC enable, DAC disable 3V No load, f SYS=4MHz, 5V RTC enable, DAC enable Operating Current 3V No load, f SYS=8MHz, 5V RTC enable, DAC enable 3V No load, f SYS=4MHz, 5V RTC disable, DAC disable Operating Current 3V No load, f SYS=8MHz, 5V RTC disable, DAC disable 3V No load, f SYS=4MHz, 5V RTC disable, DAC enable Operating Current 3V No load, f SYS=8MHz, 5V RTC disable, DAC enable ISTB1 Standby Current 3V No load, system HALT, 5V WDT enable, RTC enable 3V No load, system HALT, 5V WDT disable, RTC enable 3V No load, system HALT, 5V WDT enable, RTC disable 3V No load, system HALT, 5V WDT disable, RTC disable 3/4 3/4 3/4 Min. Typ. Max.
Ta=25C Unit V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V
IDD1
IDD2
IDD3
IDD4
ISTB2
Standby Current
ISTB3
Standby Current
ISTB4 VIL1 VIH1
Standby Current Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports 3/4
Rev. 1.00
11
March 19, 2010
HT86Axx/HT86ARxx
Test Conditions Symbol VIL2 VIH2 VLVR VLVD1 VLVD2 VLVD3 VLVD4 Parameter VDD Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset Low Voltage Detect Low Voltage Detect Low Voltage Detect Low Voltage Detect I/O Port Sink Current (For PA0~PA7, PB0~PB7, PC0~PC7, PD4~PD7, PE0~PE7) I/O Port Source Current (For PA0~PA7, PB0~PB7, PC0~PC7, PD4~PD7, PE0~PE7) I/O Port Sink Current (For PD0~PD3) I/O Port Source Current (For PD0~PD3) AUD Source Current 5V RPH VAD VREF 3V Pull-high Resistance 5V A/D Input/Output ADC Input Reference Voltage Range ADC Differential Non-Linear ADC Integral Non-Linear 3/4 3V AVDD=3V 5V AVDD=5V 3/4 3/4 3/4 3V 5V No load, tAD=1ms AVDD=5V, VREF=AVDD, tAD=1ms AVDD=5V, VREF=AVDD, tAD=1ms 3/4 3/4 3/4 3/4 3/4 Conditions 3/4 3/4 0 0.9VDD 2.0 1.9 2.0 2.1 2.2 4 VOL=0.1VDD 5V 3V VOH=0.9VDD 5V 3V 5V 3V 5V 3V VOH=0.9VDD VOH=0.9VDD VOL=0.1VDD -5 8 20 -2 -5 -1.5 -3 20 10 0 1.3 1.5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 60 30 3/4 3/4 3/4 3/4 2.5 3/4 0.5 1.5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 100 50 VREF AVDD AVDD 2.0 4.0 12 1.0 3.0 mA mA mA mA mA mA mA kW kW V V V LSB LSB bits mA mA 10 -2 3/4 3/4 3/4 3/4 mA mA 3/4 3/4 2.1 3/4 3/4 3/4 3/4 3/4 0.4VDD VDD 2.2 2.5 2.6 2.7 2.8 3/4 V V V V V V V mA Min. Typ. Max. Unit
3/4 LVR 2.1V option 3/4 LVD 2.2V 3/4 LVD 2.3V 3/4 LVD 2.4V 3/4 LVD 2.5V 3V
IOL1
IOH1
IOL2
IOH2
IAUD
DNL INL
RESOLU Resolution IADC Additional Power Consumption if A/D Converter is Used
Rev. 1.00
12
March 19, 2010
HT86Axx/HT86ARxx
A.C. Characteristics
Test Conditions Symbol fSYS Parameter VDD System Clock (RC OSC, Crystal OSC) Watchdog Oscillator Period 5V tRES tSST tLVR tINT tAD tADC tADC tMAT External Reset Low Pulse Width System Start-up Timer Period Low Voltage Reset Time Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time Circumscribe Memory Access Time 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3V Conditions HT86AXX:2.0V~5.5V HT86ARXX:2.2V~5.5V 3/4 3/4 3/4 Power-up or Wake-up from HALT 3/4 3/4 3/4 3/4 3/4 HT86AXX:2.0V~5.5V HT86ARXX:2.2V~5.5V 4 45 32 1 3/4 2 1 1.0 3/4 3/4 3/4 3/4 90 65 3/4 1024 3/4 3/4 3/4 80 32 3/4 8 180 130 3/4 3/4 3/4 3/4 3/4 3/4 3/4 400 MHz ms ms ms *tSYS ms ms ms tAD tAD ns Min. Typ. Max. Unit Ta=25C
tWDTOSC
Note: *tSYS=1/fSYS
Characteristics Curves
HT86AXX
* R vs. F Chart Characteristics Curves
R v s . F C h a rt
10 F re q u e n c y (M H z ) 8 6 4 .5 V 4 2 3 .0 V
146
188 R
276 (k W )
357
409
* T vs. F Chart Characteristics Curves
T v s . F C h a rt
1 .1 5 1 .1 1 1 .0 7 (2 5 C ) V
SC
DD
=3V
1 .0 3 0 .9 9 V 0 .9 5
DD
V
DD
=5V
fO
SC
=3V
fO
V
-6 0 -4 0
DD
=5V
0 20
T (C )
0 .9 1
-2 0
40
60
80
100
Rev. 1.00
13
March 19, 2010
HT86Axx/HT86ARxx
* V vs. F Chart Characteristics Curves - 3.0V
V v s . F C h a r t (F o r 3 .0 V )
10 8 6 4 2
4 M H z /2 7 6 k W 8 M H z /1 4 6 k W 6 M H z /1 8 8 k W
F re q u e n c y (M H z )
2 .2
2 .6
3 .0
3 .3
3 .8 V
DD
4 .2 (V )
4 .5
4 .9
5 .2
5 .5
* V vs. F Chart Characteristics Curves - 4.5V
V v s . F C h a r t (F o r 4 .5 V )
10 8 6 4 2
8 M H z /1 4 0 k W 6 M H z /1 8 7 k W
F re q u e n c y (M H z )
4 M H z /2 6 9 k W
2 .2
2 .6
3 .0
3 .3
3 .8 V
DD
(V )
4 .2
4 .5
4 .9
5 .2
5 .5
HT86ARXX
* R vs. F Chart Characteristics Curves
R v s . F C h a rt
10 F re q u e n c y (M H z ) 8 6 4 2 4 .5 V
3 .0 V
49
61 R
86 (k W )
111
132
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* T vs. F Chart Characteristics Curves
T v s . F C h a rt
1 .1 0 1 .0 8 1 .0 6 (2 5 C ) 1 .0 4 1 .0 2 1 .0 0 0 .9 8 0 .9 6 0 .9 4 -6 0 -4 0 -2 0 0 20
T (C )
V
DD
=3V
fO
V V
DD
DD
=5V
SC
=5V
V
DD
fO
SC
=3V
40
60
80
100
* V vs. F Chart Characteristics Curves - 3.0V
V v s . F C h a r t (F o r 3 .0 V )
10 8 6 4 2
8 M H z /4 9 k W 6 M H z /6 1 k W
F re q u e n c y (M H z )
4 M H z /8 6 k W
2 .2
2 .6
3 .0
3 .3
3 .8 V
DD
4 .2 (V )
4 .5
4 .9
5 .2
5 .5
* V vs. F Chart Characteristics Curves - 4.5V
V v s . F C h a r t (F o r 4 .5 V )
10 8 6 4 2
8 M H z /4 3 k W 6 M H z /5 5 k W
F re q u e n c y (M H z )
4 M H z /7 9 k W
2 .2
2 .6
3 .0
3 .3
3 .8 V
DD
(V )
4 .2
4 .5
4 .9
5 .2
5 .5
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System Architecture
A key factor in the high-performance features of the Holtek range of Voice microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O, voltage type DAC, capacitor/resistor sensor input and external RC oscillator converter with maximum reliability and flexibility. Clocking and Pipelining The main system clock, derived from either a Crystal/ Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The
O s c illa to r C lo c k ( S y s te m C lo c k ) P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r PC PC+1 PC+2
Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. When the RC oscillator is used, OSC2 is freed for use as a T1 phase clock synchronizing pin. This T1 phase clock has a frequency of fSYS/4 with a 1:3 high/low duty cycle. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
P ip e lin in g
F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 2 3 4 5 6 D ELAY: : :
M O V A ,[1 2 H ] C ALL D ELAY C P L [1 2 H ]
F e tc h In s t. 1
E x e c u te In s t. 1 F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7
NOP
Instruction Fetching
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Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as JMP or CALL, that demand a jump to a non-consecutive Program Memory address. Note that the Program Counter width varies with the Program Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
P ro g ra m
C o u n te r
T o p o f S ta c k S ta c k P o in te r
S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k L e v e l 3 P ro g ra m M e m o ry
B o tto m
o f S ta c k
S ta c k L e v e l 8
Program Counter Mode *12 Initial Reset External Interrupt Timer 0 Overflow Timer 1 Overflow Timer 2 Overflow Timer 3 Overflow A/D Converter Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine *12 #12 *11 #11 *10 #10 *9 #9 S9 *8 #8 S8 0 0 0 0 0 0 0 *11 0 0 0 0 0 0 0 *10 0 0 0 0 0 0 0 *9 0 0 0 0 0 0 0 *8 0 0 0 0 0 0 0 *7 0 0 0 0 0 0 0 *6 0 0 0 0 0 0 0 *5 0 0 0 0 0 0 0 *4 0 0 0 0 1 1 1 *3 0 0 1 1 0 0 1 *2 0 1 0 1 0 1 0 *1 0 0 0 0 0 0 0 *0 0 0 0 0 0 0 0
Program Counter + 2 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
S12 S11 S10
Program Counter Note: *12~*0: Program counter bits #12~#0: Instruction code bits S12~S0: Stack register bits @7~@0: PCL bits
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If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:
* Arithmetic operations ADD, ADDM, ADC, ADCM, * Location 004H
This vector is used by the external interrupt. If the external interrupt pin on the device goes low, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full.
* Location 008H
This internal vector is used by the 8-bit Timer 0. If a overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.
* Location 00CH
This internal vector is used by the 8-bit Timer1. If a overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.
* Location 010H
This internal vector is used by the 8-bit Timer2. If a overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.
* Location 014H
SUB, SUBM, SBC, SBCM, DAA
* Logic operations AND, OR, XOR, ANDM, ORM,
This internal vector is used by the 8-bit Timer3. If a overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.
* Location 018H
XORM, CPL, CPLA
* Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
* Increment and Decrement INCA, INC, DECA, DEC * Branch decision JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA,
This internal vector is used by the A/D Converter. If an A/D converter conversion completes, the program will jump to this location and begin execution if the A/D converter interrupt is enabled and the stack is not full.
000H 004H In itia lis a tio n V e c to r E x te rn a l In te rru p t V e c to r T im e r 0 In te rru p t V e c to r T im e r 1 In te rru p t V e c to r T im e r 2 In te rru p t V e c to r T im e r 3 In te rru p t V e c to r A /D C o n v e rte r In te rru p t V e c to r
SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user code or program is stored. Structure The program memory stores the program instructions that are to be executed. It also includes data, table and interrupt entries, addressed by the Program Counter along with the table pointer. The program memory size is 819216 bits. Certain locations in the program memory are reserved for special usage. Special Vectors Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
* Location 000H
010H 014H 018H 019H 1FFFH 008H 00CH
1 6 b its
Program Memory Structure
This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution.
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Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, table pointers are used to setup the address of the data that is to be accessed from the Program Memory. However, as some devices possess only a low byte table pointer and other devices possess both a high and low byte pointer it should be noted that depending upon which device is used, accessing look-up table data is implemented in slightly different ways. For the devices, there are two Table Pointer Registers known as TBLP and TBHP in which the lower order and higher order address of the look-up data to be retrieved must be respectively first written. Unlike the other devices in which only the low address byte is defined using the TBLP register, the additional TBHP register allows the complete address of the look-up table to be defined and consequently allow table data from any address and any page to be directly accessed. For these devices, after setting up both the low and high byte table pointers, the table data can then be retrieved from any area of Program Memory using the TABRDC [m] instruction or from the last page of the Program Memory using the TABRDL [m] instruction. When either of these instructions are executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0. tempreg1 tempreg2 db db : : a,06h tblp,a : : tempreg1 ? ? The following diagram illustrates the addressing/data flow of the look-up table for the devices:
TBHP TBLP P ro g ra m M e m o ry
TBLH H ig h B y te o f T a b le C o n te n ts
S p e c ifie d b y [m ] Low B y te o f T a b le C o n te n ts
Look-up Table Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the devices. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is 1F00H which refers to the start address of the last page within the Program Memory of the microcontroller. The table pointer is setup here to have an initial value of 06H. This will ensure that the first data read from the data table will be at the Program Memory address 1F06H or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the TABRDC [m] instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRDL [m] instruction is executed.
; temporary register #1 ; temporary register #2
mov mov
; initialise table pointer - note that this address ; is referenced ; to the last page or present page
tabrdl
; ; ; ;
transfers value in table referenced by table pointer to tempregl data at prog. memory address 1F06H transferred to tempreg1 and TBLH
dec tabrdl
tblp tempreg2
; reduce value of table pointer by one ; ; ; ; ; ; ; ; transfers value in table referenced by table pointer to tempreg2 data at prog.memory address 1F05H transferred to tempreg2 and TBLH in this example the data 1AH is transferred to tempreg1 and data 0FH to register tempreg2 the value 00H will be transferred to the high byte register TBLH
: : org dc 1F00h ; sets initial address of HT86A72 last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : 19 March 19, 2010
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Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Location Instruction *12 TABRDC [m] TABRDL [m] P12 1 *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: *12~*0: Current Program ROM table @7~@0: Write @7~@0 to TBLP pointer register P12~P8: Write P12~P8 to TBHP pointer register
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of RAM Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Structure The Data Memory is subdivided into two banks, known as Bank 0 and Bank 1, all of which are implemented in 8-bit wide RAM. Most of the RAM Data Memory is located in Bank 0 which is also subdivided into two sections, the Special Purpose Data Memory and the General Purpose Data Memory. The start address of the RAM Data Memory for all devices is the address 00H, and the last Data Memory address is FFH. Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. Note: Most of the RAM Data Memory bits can be directly manipulated using the SET [m].i and CLR [m].i instructions with the exception of a few dedicated bits. The RAM Data Memory can also be accessed through the Memory Pointer registers MP0 and MP1. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the SET [m].i and CLR [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory.
00H S p e c ia l P u r p o s e D a ta M e m o ry 3EH 40H G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s ) Bank 0 :U nknow 40H G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s ) Bank 1
FFH
FFH
RAM Data Memory Structure - Bank 0 and Bank 1
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Special Purpose Data Memory This area of Data Memory, is located in Bank 0, where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH L L L L R0 P0 R1 P1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C TM R0 TM R0C TM R1 TM R1C PA PAC PB PBC PC PCC ATCH0 ATCH0 ATCH0 ATCH1 ATCH1 ATCH1 IN T C H TBHP L M M H L TM R2 TM R2C TM R3 TM R3C V O IC E C DAL DAH VOL LATCHD IA M IA M
the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value 00H. Although the Special Purpose Data Memory registers are located in Bank 0, they will still be accessible even if the Bank Pointer has selected Bank 1.
Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in the RAM Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, watchdog, etc., as well as external functions such as I/O data control. The location of these registers within the RAM Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of 00H. Indirect Addressing Register - IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together only access data from Bank 0, while the IAR1 and MP1 register pair can access data from both Bank 0 and Bank 1. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation.
L
L
H
PD PDC ADRL ADRH ADCR ACSR LVDC
Memory Pointer - MP0, MP1 For all devices, two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0 only, while MP1 and IAR1 are used to access data from both Bank 0 and Bank 1.
P PE SB SB
C CR DR :U nknow
E
Special Purpose Data Memory Structure
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The following example shows how to clear a section of four RAM locations already defined as locations adres1 to adres4. data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov mov mov mov loop: clr inc sdz jmp continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. IAR0 mp0 block loop ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared a,04h ; setup size of block block,a a,offset adres1; Accumulator loaded with first RAM address mp0,a ; setup memory pointer with first RAM address
Bank Pointer - BP The RAM Data Memory is divided into two Banks, known as Bank 0 and Bank 1. With the exception of the BP register, all of the Special Purpose Registers and General Purpose Registers are contained in Bank 0. If data in Bank 0 is to be accessed, then the BP register must be loaded with the value "00", while if data in Bank 1 is to be accessed, then the BP register must be loaded with the value 01. Using Memory Pointer MP0 and Indirect Addressing Register IAR0 will always access data from Bank 0, irrespective of the value of the Bank Pointer. The Data Memory is initialised to Bank 0 after a reset, except for the WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within either Bank 0 or Bank 1. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted.
b7
b0 BP0
B a n k P o in te r BP0 0 1 D a ta M e m o ry Bank 0 Bank 1
N o t u s e d , m u s t b e re s e t to "0 "
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Look-up Table Registers - TBLP, TBHP, TBLH These two special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates the location where the table data is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the INC or DEC instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Watchdog Timer Register - WDTS The Watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect Program Memory addresses. To implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows. To provide variable Watchdog Timer reset times, the Watchdog Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register. By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT
b7 TO PDF OV Z AC
time-out or by executing the CLR WDT or HALT instruction. The PDF flag is affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations.
* C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
* AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
* Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
* OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
* PDF is cleared by a system power-up or executing the
CLR WDT instruction. PDF is set by executing the HALT instruction.
* TO is cleared by a system power-up or executing the
CLR WDT or HALT instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Interrupt Control Register - INTC, INTCH Two 8-bit register, known as the INTC and INTCH registers, controls the operation of both external and internal timer interrupts. By setting various bits within these registers using standard bit manipulation instructions, the enable/disable function of the external and timer interrupts can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt
b0 C
S T A T U S R e g is te r
Ar Ca Au Ze ith m e r r y fla x ilia r y r o fla g O v e r flo w g tic /L o g ic O p e r a tio n F la g s c a r r y fla g fla g an n tim e a g e m e n t F la g s fla g e - o u t fla g n te d , re a d a s "0 "
S y s te m M Pow erdow W a tc h d o g N o t im p le m
Status Register
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routine is entered to disable further interrupt and is set by executing the RETI instruction. Note: In situations where other interrupts may require servicing within present interrupt service routines, the EMI bit can be manually set by the program after the present interrupt service routine has been entered. Timer Registers All devices contain four 8-bit Timers whose associated registers are known as TMR0, TMR1, TMR2 and TMR3, which are the locations where the associated timer's 8-bit value is located. Their associated control registers, known as TMR0C, TMR1C, TMR2C and TMR3C, contain the setup information for these timers. Note that all timer registers can be directly written to in order to preload their contents with fixed data to allow different time intervals to be setup. Input/Output Ports and Control Registers Within the area of Special Function Registers, the I/O registers and their associated control registers play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB, PC, PD, PE, etc. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC, PBC, PCC, PDC, PEC, etc., also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. During program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the SET [m].i and CLR [m].i instructions. The ability to change I/O pins from output to input and vice-versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices. Voice ROM Data Address Latch Counter Registers These are the LATCH0H/LATCH0M/LATCH0L, LATCH1H/LATCH1M/LATCH1L and the Voice ROM data registers. The voice ROM data address latch count e r p ro vi d e s t h e h a n d s hak i ng b e t w e e n t h e microcontroller and the voice ROM, where the voice codes are stored. Eight bits of voice ROM data will be addressed by using the 21-bit address latch counter, which is composed of LATCH0H/LATCH0M/LATCH0L or LATCH1H/LATCH1M/LATCH1L. After the 8-bit voice ROM data is addressed, several instruction cycles of at least 4ms at least, will be required to latch the voice ROM data, after which the microcontroller can read the voice data from LATCHD. Voice Control and Audio output Registers VOICEC, DAL, DAH, VOL The device includes a single 12-bit current type DAC function for driving an external 8W speaker through an external NPN transistor. The programmer must write the voice data to the DAL/DAH registers. A/D Converter Registers ADRL, ADRH, ADCR, ACSR The device contains a 4-channel 12-bit A/D converter. The correct operation of the A/D requires the use of two data registers, a control register and a clock source register. It contain a 12-bit A/D converter, there are two data registers, a high byte data register known as ADRH, and a low byte data register known as ADRL. These are the register locations where the digital value is placed after the completion of an analog to digital conversion cycle. The channel selection and configuration of the A/D converter is setup via the control register ADCR while the A/D clock frequency is defined by the clock source register, ACSR.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. Depending upon which device or package is chosen, the microcontroller range provides 40 bidirectional input/output lines labeled with port names PA, PB, PC, PD, PE, etc. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction MOV A,[m], where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selectable via configuration options and are implemented using a weak PMOS transistor. Note that if the pull-high option is
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selected, then all I/O pins on that port will be connected to pull-high resistors, individual pins can be selected for pull-high resistor options. Port A Wake-up Each device has a HALT instruction enabling the microcontroller to enter a Power Down Mode and preserve power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. After a HALT instruction forces the microcontroller into entering a HALT condition, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on Port A changes from high to low. This function is especially suitable for applications that can be woken up via external switches. Note that each pin on Port A can be selected individually to have this wake-up feature. I/O Port Control Registers Each I/O port has its own control register PAC, PBC, PCC, PDC, PEC, etc., to control the input/output configuration. With this control register, each CMOS output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a 1. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a 0, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control.
* A/D Inputs
There are no configuration options associated with the A/D function. If used as I/O pins, then full pull-high resistor selections remain, however if used as A/D inputs then any pull-high resistor selections associated with these pins will be automatically disconnected.
* Serial Interface
The Serial Interface are pin-shared with PD0 to PD3. If there are to be used as Serial Interface inputs and not as normal I/O pins then the corresponding bits in the Serial Interface Control Register that must be properly set. There are a configuration option associated with the Serial Interface function. If used as I/O pins, then full pull-high resistor selections remain, however if used as the Serial Interface inputs then any pull-high resistor selections associated with these pins will be automatically disconnected.
* I/O Pin Structures
The following diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. Note also that the specified pins refer to the largest device package, therefore not all pins specified will exist on all devices. Programming Considerations Within the user program, one of the first things to consider is port initialization. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the port control registers, PAC, PBC, PCC, PDC, PEC etc., are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA, PB, PC, PD, PE, etc., are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the SET [m].i and CLR [m].i instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
T1 S y s te m C lo c k T2 T3 T4 T1 T2 T3 T4
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
The device have 4 A/D converter channel inputs. All of these analog inputs are pin-shared with PC0 to PC3. If these pins are to be used as A/D inputs and not as normal I/O pins then the corresponding bits in the A/D Converter Control Register that must be properly set.
Read/Write Timing
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V C o n tr o l B it D a ta B u s D CK S Q W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it Q D W r ite D a ta R e g is te r CK S Q M U X W a k e - u p O p tio n R e a d D a ta R e g is te r S y s te m W a k e -u p PA0~PA7 Q P u ll- H ig h O p tio n
DD
W eak P u ll- u p
PA Input/Output Port
V C o n tr o l B it D a ta B u s D CK S W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it D W r ite D a ta R e g is te r CK S Q Q M U X R e a d D a ta R e g is te r Q Q P u ll- H ig h O p tio n
DD
W eak P u ll- u p
PB0~PB7 PE0~PE7
PB/PE Input/Output Ports
V C o n tr o l B it D a ta B u s D CK S W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it D W r ite D a ta R e g is te r CK S Q Q
M U X
DD
Q Q
P u ll- H ig h O p tio n
W eak P u ll- u p
PC 0~PC 7 AD 0~AD 3
P C 0 D a ta B it AD 0~AD 3 M U X R e a d D a ta R e g is te r
A /D
C o n v e rte r
PC Input/Output Port Rev. 1.00 26 March 19, 2010
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V C o n tr o l B it D a ta B u s D CK S W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it D W r ite D a ta R e g is te r CK S Q Q
M U X
DD
Q Q
P u ll- H ig h O p tio n
W eak P u ll- u p
PD 0~PD 7 S C S , S C K , S D I, S D O
P D 0 D a ta B it S C S , S C K , S D I, S D O M U X R e a d D a ta R e g is te r
S e r ia l In te r fa c e
PD Input/Output Port
Port A has the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.
Timers
The provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. The devices in the Voice Type MCU series contain four count up timers of 8-bit capacity. Each timer has only one operating mode, which is to act as a general timer. The provision of an internal prescaler to the clock circuitry of the timers gives added range to the timer. Configuring the Timer Input Clock Source The clock source of Timer0/Timer1/Tmier2 is the system clock divided by four and the clock source of Timer3 is
the system clock divided by four or the RTC clock which is derived from a external 32kHz crystal. A configuration option determines which clock is selected. If the RTC clock is selected then note that it will continue to run when the device is powered down using the HALT instruction. The 8-bit timer clock source is also first divided by a prescaler, the division ratio of which is conditioned by the three lower bits of the associated timer control register. Timer Registers - TMR0, TMR1, TMR2, TMR3 The timer registers are special function registers located in the special purpose Data Memory and is the place where the actual timer value is stored. The value in the timer registers increases by one each time an internal clock pulse is received. The timer will count from the initial value loaded by the preload register to the full count of FFH at which point the timer overflows and an internal interrupt signal is generated. The timer value will then be reset with the initial preload register value and continue counting.
D a ta B u s P r e lo a d R e g is te r R e lo a d
T2PSC 2~T2PSC 0 T1PSC 2~T1PSC 0 T0PSC 2~T0PSC 0 fS
YS
T2TM 1 T1TM 1 T0TM 1
T2TM 0 T1TM 0 T0TM 0
/4
P r e s c a le r (1 /2 ~ 1 /2 5 6 )
T im e r M o d e C o n tr o l T0O N T1O N T2O N
T im e r 8 - B it T im e r
O v e r flo w to In te rru p t
8-bit Timer Structure - TMR0, TMR1, TMR2
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D a ta B u s P r e lo a d R e g is te r C o n fig u r a tio n O p tio n fS
Y S /4 RTC
R e lo a d
T3PSC 2~T3PSC 0 P r e s c a le r (1 /2 ~ 1 /2 5 6 )
T3TM 1
T3TM 0 T im e r T3O N 8 - B it T im e r O v e r flo w to In te rru p t
MUX
T im e r M o d e C o n tr o l
8-bit Timer Structure - TMR3
Note that to achieve a maximum full range count of FFH for the 8-bit timer, the preload registers must first be cleared to all zeros. It should be noted that after power-on, the preload registers will be in an unknown condition. Note that if the Timer Counters are in an OFF condition and data is written to their preload registers, this data will be immediately written into the actual counter. However, if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overflow occurs. Note also that when the timer registers are read, the timer clock will be blocked to avoid errors, however, as this may result in certain timing errors, programmers must take this into account. Timer Control Registers TMR0C, TMR1C, TMR2C, TMR3C The timers are setup using their respective control register. These registers are known as TMR0C, TMR1C, TMR2C and TMR3C. It is the timer control register together with its corresponding timer registers that control the full operation of the Timer. Before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialization. Bits 7 and 6 of the Timer Control Register, which are known as the bit pair TM1/TM0, must be set to 10 respectively to ensure correct Timer operation. The
timer-on bit, which is bit 4 of the Timer Control Register and known as TON, provides the basic on/off control of the respective timer. setting the bit high allows the timer to run, clearing the bit stops the timer. Bits 0~2 of the Timer Control Register determine the division ratio of the input clock prescaler. Configuring the Timer The Timer is used to measure fixed time intervals, providing an internal interrupt signal each time the Timer overflows. To do this the Operating Mode Select bit pair in the Timer Control Register must be set to the correct value as shown. The Timer clock source is further divided by a prescaler, the value of which is determined by the Prescaler Rate Select bits, which are bits 0~2 in the Timer Control Register. After the other bits in the Timer Control Register have been setup, the enable bit, which is bit 4 of the Timer Control Register, can be set high to enable the Timer to run. Each time an internal clock cycle occurs, the Timer increments by one. When it is full and overflows, an interrupt signal is generated and the Timer will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer Interrupt Enable bit in the Interrupt Control Register, INTC, is reset to zero.
P r e s c a le r O u tp u t In c re m e n t T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N
+1
Timer Mode Timing Diagram
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b7 TM 1 TM 0 TON PSC2 PSC1 b0 PSC0 T M R 0 C /T M R 1 C /T M R 2 C /T M R 3 C T im T0 T1 T2 T3 er PSC PSC PSC PSC 0 0 0 0 1 1 1 1 P re s 2T 2T 2T 2T ca 0 1 2 3 le r PSC PSC PSC PSC 0 0 1 1 0 0 1 1 R a te T 1 T 1 T 1 T 1 Se 0P 1P 2P 3P le c SC SC SC SC 0 1 0 1 0 1 0 1 t 0 0 0 0 T im e r R a te 1 :2 1 :4 1 :8 1 :1 1 :3 1 :6 1 :1 1 :2 R e g is te r
6 4 28 56 2
N o t im p le m e n t e d , r e a d a s " d o n 't c a r e " T im e r o n /o ff c o n tr o l 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " Op T0 T1 T2 T3 er TM TM TM TM 0 0 1 1 a tin g M T 1 T 1 T 1 T 1 od 0T 1T 2T 3T 0 1 0 1 e S e le c t M0 M0 M0 M0 no no tim no
m od m od erm m od
e a v a ila b le e a v a ila b le ode e a v a ila b le
Timer Control Register - All Devices
Prescaler All of the 8-bit timers possess a prescaler. Bits 0~2 of their associated timer control register, define the pre-scaling stages of the internal clock source of the Timer. The Timer overflow signal can be used to generate signals for the Timer interrupt. Programming Considerations The internal system clock is used as the timer clock source and is therefore synchronized with the overall operation of the microcontroller. In this mode, when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. When the Timer is read, the clock is blocked to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer enable bits in the interrupt control register
must be properly set otherwise the internal interrupt associated with the timer will remain inactive. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. Timer Program Example The following example program section is based on the devices, which contain a single internal 8-bit timer. Programming the timer for other devices is conducted in a very similar way. The program shows how the timer registers are setup along with how the interrupts are enabled and managed. Also note how the timer is turned on by setting bit 4 of the respective timer control register. The timer can be turned off in a similar way by clearing the same bit. This example program sets the timer to be in the timer mode which uses the internal system clock as their clock source.
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include HT86A72.inc jmp begin : org 04h ; external interrupt vectors reti org 08h reti org 0Ch reti org 10h ; timer 2 interrupt vector jmp tmr2int ; jump here when timer 2 overflows org 14h reti org 18h reti : ; internal timer 2 interrupt routine tmr2int: : ; timer 2 main program placed here : reti : begin: ; setup timer 2 registers mov a,09bh ; setup timer 2 mov tmr2,a mov a,0097h ; setup timer 2 mov tmr2c,a ; setup timer 2 ; setup interrupt register mov a,01h ; enable master interrupt mov intc,a mov a,01h ; enable timer 2 interrupt mov intch,a :
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Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer requires microcontroller attention, their corresponding interrupt will enforce a temporary susp e n s io n o f t h e m a i n pr o g r am al l ow i n g t h e microcontroller to direct attention to their respective needs. Interrupt Register Overall interrupt control, which means interrupt enabling and flag setting, is controlled using two registers, known as INTC and INTCH, which are located in the Data Memory. By controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. Interrupt Operation A timer overflow or the external interrupt line being pulled low will all generate an interrupt request by setting their corresponding request flag, if their appropriate interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will take program execution to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI statement, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagram with their order of priority. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full.
b7 T1F T0F E IF
ET1I
b0 ET0I EEI EMI IN T C R e g is te r M a s te r In te r r u p t G lo b a l E n a b le 1 : g lo b a l e n a b le 0 : g lo b a l d is a b le E x te r n a l In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le T im e r 0 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le T im e r 1 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le E x te r n a l In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r 0 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r 1 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e N o im p le m e n te d , r e a d a s " 0 "
Interrupt Control Register
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b7 ADF T3F T2F EADI b0
ET3I ET2I
IN T C H
R e g is te r
T im e r 2 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le T im e r 3 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le A /D C o n v e r te r In te r r u p t E n a b le
N o im p le m e n te d , r e a d a s " 0 " T im e r 2 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r 3 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e A /D C o n v e r te r In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e N o im p le m e n te d , r e a d a s " 0 "
INTCH Register
A u to m a tic a lly C le a r e d b y IS R M a n u a lly S e t o r C le a r e d b y S o ftw a r e E x te rn a l In te rru p t R e q u e s t F la g E IF T im e r 0 In te r r u p t R e q u e s t F la g T 0 F T im e r 1 In te r r u p t R e q u e s t F la g T 1 F T im e r 2 In te r r u p t R e q u e s t F la g T 2 F T im e r 3 In te r r u p t R e q u e s t F la g T 3 F A /D C o n v e rte r In te r r u p t R e q u e s t F la g A D F EEI
A u to m a tic a lly D is a b le d b y IS R C a n b e E n a b le d M a n u a lly P r io r ity EMI H ig h
ET0I
ET1I
ET2I
In te rru p t P o llin g
ET3I
EADI
Low
Interrupt Structure
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Interrupt Priority Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the accompanying table shows the priority that is applied. Interrupt Source External Interrupt Timer 0 Overflow Timer 1 Overflow Timer 2 Overflow Timer 3 Overflow A/D Converter Overflow Interrupt Vector Priority 04H 08H 0CH 10H 14H 18H 1 2 3 4 5 6 Each timer also has a corresponding timer interrupt request flag, which are known as T0F, T1F, T2F and T3F, also located in the INTC and INTCH registers. When the master interrupt and corresponding timer interrupt enable bits are enabled, the stack is not full, and when the corresponding timer overflows a subroutine call to the corresponding timer interrupt vector will occur. The corresponding Program Memory vector locations for Timer 0, Timer1, Timer 2 and Timer 3 are 08H, 0CH, 10H and 14H. After entering the interrupt execution routine, the corresponding interrupt request flags, T0F, T1F, T2F or T3F will be reset and the EMI bit will be cleared to disable other interrupts. A/D Converter Interrupt The internal A/D Converter interrupt is initialised by setting the A/D interrupt request flag (ADF:bit6 of INTCH). When the interrupt is enabled, and the stack is not full and the ADF bit is set, a subroutine call to location 18H will occur. The related interrupt request flag, ADF, will be reset and the EMI bit cleared to disable further interrupts. Programming Considerations By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the INTC or INTCH register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. It is recommended that programs do not use the CALL subroutine instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the MCU when in the Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance.
In cases where both external the timer interrupts are enabled and where an external and timer interrupt occur simultaneously, the external interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the INTC and INTCH registers can prevent simultaneous occurrences. External Interrupt Each device contains a single external interrupt function controlled by the external pin, INT. For an external interrupt to occur, the corresponding external interrupt enable bit must be first set. This is bit 1 of the INTC register and known as EEI. An external interrupt is triggered by an external edge transition on the external interrupt pin INT, after which the related interrupt request flag, EIF, which is bit 4 of INTC, will be set. A configuration option exists for the external interrupt pin to determine the type of external edge transition which will trigger an external interrupt. There are two options available, a low going edge or both high and low going edges. When the master interrupt and external interrupt bits are enabled, the stack is not full and an active edge transition, as setup in the configuration options, occurs on the INT pin, a subroutine call to the corresponding external interrupt vector, which is located at 04H, will occur. After entering the interrupt execution routine, the corresponding interrupt request flag, EIF, will be reset and the EMI bit will be cleared to disable other interrupts. Timer Interrupt For a timer generated interrupt to occur, the corresponding timer interrupt enable bit must be first set. Each device contains four 8-bit timers whose corresponding interrupt enable bits are known as ET0I, ET1I, ET2I and ET3I and are located in the INTC and INTCH registers.
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Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally:
* Power-on Reset
inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer.
VDD RES S S T T im e - o u t In te rn a l R e s e t 0 .9 V tR
DD
STD
Power-On Reset Timing Chart For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference.
VDD 100kW RES 0 .1 m F VSS
Basic Reset Circuit For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended.
0 .0 1 m F 100kW RES
10kW
VDD
0 .1 m F VSS
The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be
Enhanced Reset Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website.
* RES Pin Reset
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initiated from this point.
RES S S T T im e - o u t In te rn a l R e s e t 0 .4 V 0 .9 V
DD DD
tR
STD
RES Reset Timing Chart Rev. 1.00 34 March 19, 2010
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* Low Voltage Reset - LVR
Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 u 1 0 u u 1 RESET Conditions RES reset during power-on RES or LVR reset during normal operation WDT time-out reset during normal operation WDT time-out reset during Power Down
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
LVR tR S S T T im e - o u t In te rn a l R e s e t
STD
1
Note: u stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Program Counter Interrupts WDT Timer Prescaler Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting All Timer will be turned off The Timer Prescaler will be cleared
Low Voltage Reset Timing Chart
* Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to 1.
W D T T im e - o u t
tR
S S T T im e - o u t In te rn a l R e s e t
STD
WDT Time-out Reset during Normal Operation Timing Chart
* Watchdog Time-out Reset during Power Down
Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack
The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1. Refer to the A.C. Characteristics for tSST details.
W D T T im e - o u t
tS
S S T T im e - o u t
ST
WDT Time-out Reset during Power Down Timing Chart
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The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. Register MP0 MP1 BP ACC PCL TBLP TBLH WDTS STATUS INTC TMR0 TMR0C TMR1 TMR1C PA PAC PB PBC PC PCC PD PDC PE PEC TMR2 TMR2C TMR3 TMR3C INTCH TBHP DAL DAH VOL VOICEC Reset (Power-on) xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx 0000 0111
--00 xxxx
WDT Time-out RES Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 -- 1u uuuu -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 00-0 1000 0000 0000 00-0 1000 -000 -000 uuuu uuuu uuuu ---uuuu uuuu xxx- ---0000 -00uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 --uu uuuu -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 00-0 1000 0000 0000 00-0 1000 -000 -000 uuuu uuuu uuuu ---uuuu uuuu xxx- ---0000 -00-
RES Reset (HALT) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 -- 01 uuuu -000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 00-0 1000 0000 0000 00-0 1000 -000 -000 uuuu uuuu uuuu ---uuuu uuuu xxx- ---0000 -00-
WDT Time-out from HALT uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uu-u uuuu -uuu -uuu uuuu uuuu uuuu ---uuuu uuuu uuu- ---uuuu -uu-
-000 0000 0000 0000 00-0 1000 0000 0000 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 00-0 1000 0000 0000 00-0 1000 -000 -000 xxxx xxxx xxxx ---xxxx xxxx xxx- ---0000 -00-
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Register LATCH0H LATCH0M LATCH0L LATCH1H LATCH1M LATCH1L LATCHD ADRL ADRH ADCR ACSR LVDC SBCR SBDR Reset (Power-on) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---xxxx xxxx 0100 0000 ---- --00 000x 0-00 0110 0000 xxxx xxxx WDT Time-out RES Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx ---xxxx xxxx 0100 0000 ---- --00 000x 0-00 0110 0000 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx ---xxxx xxxx 0100 0000 ---- --00 000x 0-00 0110 0000 xxxx xxxx RES Reset (HALT) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx ---xxxx xxxx 0100 0000 ---- --00 000x 0-00 0110 0000 xxxx xxxx WDT Time-out from HALT uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---uuuu uuuu uuuu uuuu ---- --uu uuux u-uu uuuu uuuu uuuu uuuu
Note: u stands for unchanged x stands for unknown - stands for undefined
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Oscillator
Various oscillator options offer the user a wide range of functions according to their various application requirements. Two types of system clocks can be selected while various clock source options for the Watchdog Timer are provided for maximum flexibility. All oscillator options are selected through the configuration options. The two methods of generating the system clock are:
* External crystal/resonator oscillator * External RC oscillator
One of these two methods must be selected using the configuration options. More information regarding the oscillator is located in Application Note HA0075E on the Holtek website. External Crystal/Resonator Oscillator The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. However, for some crystals and most resonator types, to ensure oscillation and accurate frequency generation, it may be necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation
C1 Rp In te r n a l O s c illa to r C ir c u it
OSC1 and VSS. A clock signal, with a frequency of the generated system clock divided by 4, will be provided on OSC2 as an output which can be used for external synchronisation purposes. Note that as the OSC2 output is an NMOS open-drain type, a pull high resistor should be connected if it to be used to monitor the internal frequency. Although this is a cost effective oscillator configuration, the oscillation frequency can vary with VDD, temperature and process variations and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies are required. Note that it is the only microcontroller internal circuitry together with the external resistor, that determines the frequency of the oscillator.
OSC1 R fS
YS OSC
/4 N M O S O p e n D r a in
OSC2
External RC Oscillator Watchdog Timer Oscillator The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period of 65ms at 5V requiring no external components. When the device enters the Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option. RTC Oscillator A 32KHz crystal can be connected to pins XIN and XOUT to implement an RTC oscillator. The RTC oscillator is used as a clock source for Timer/Event Counter 3 but must be first enabled using a configuration option. If the configuration option enables the RTC oscillator then it will automatically become the clock source for the Timer/Event Counter 3. The RTC oscillator will continue to operate even if the HALT instruction is executed and the device is powered down. It may be necessary to connect two small capacitors between XIN, XOUT and ground for correct operation of the RTC.
32768Hz
OSC1 Rf Ca
Cb C2 OSC2
T o in te r n a l c ir c u its
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . 2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator with the crystal or resonator manufacturers specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to assist with oscillation start up. Internal Ca, Cb, Rf Typical Values @ 5V, 25C Ca 11~13pF Cb 13~15pF Rf 800kW
Oscillator Internal Component Values External RC Oscillator Using the external system RC oscillator requires that an external resistor is connected. For the Mask version device a value of between 120kW and 280kW is required For the OPT device a value of between 40kW and 90kW is required. This external resistor is connected between
X IN
XOUT
RTC Oscillator
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Power Down Mode and Wake-up
Power Down Mode All of the Holtek microcontrollers have the ability to enter a Power Down Mode, also known as the HALT Mode or Sleep Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. This occurs because when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCU must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the HALT instruction in the application program. When this instruction is executed, the following will occur:
* The system oscillator will stop running and the appli-
Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows:
* An external reset * An external falling edge on Port A * A system interrupt * A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup via an individual configuration option to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the HALT instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled. No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal system operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or more cycles. If the wake-up results in the execution of the next instruction following the HALT instruction, this will be executed immediately after the 1024 system clock period delay has ended.
cation program will stop at the HALT instruction.
* The Data Memory contents and registers will maintain
their present condition.
* The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT oscillator. The WDT will stop if its clock source originates from the system clock.
* The I/O ports will maintain their present condition. * In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. Care must also be taken with the loads, which are connected to I/Os, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the Watchdog Timer internal oscillator.
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Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT clock is supplied by one of two sources selected by configuration option: its own self-contained dedicated internal WDT oscillator, or the instruction clock which is the system clock divided by 4. Note that if the WDT configuration option has been disabled, then any instruction relating to its operation will result in no operation. The internal WDT oscillator has an approximate period of 65ms at a supply voltage of 5V. If selected, it is first divided by 256 via an 8-stage counter to give a nominal period of 17ms. Note that this period can vary with VDD, temperature and process variations. For longer WDT time-out periods the WDT prescaler can be utilized. By writing the required value to bits 0, 1 and 2 of the WDTS register, known as WS0, WS1 and WS2, longer time-out periods can be achieved. With WS0, WS1 and WS2 all equal to 1, the division ratio is 1:128 which gives a maximum time-out period of about 2.1s. A configuration option can select the instruction clock, which is the system clock divided by 4, as the WDT clock source instead of the internal WDT oscillator. If the instruction clock is used as the clock source, it must be noted that when the system enters the Power Down Mode, as the system clock is stopped, then the WDT clock source will also be stopped. Therefore the WDT will lose its protecting purposes. In such cases the system cannot be restarted by the WDT and can only be restarted using external signals. For systems that operate in noisy environments, using the internal WDT oscillator is therefore the recommended choice. Under normal program operation, a WDT time-out will initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a WDT time-out occurs, only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the WDT and the WDT prescaler. The first is an external hardware reset, which means a low level on the RES pin, the second is using the watchdog software instructions and the third is via a HALT instruction. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single CLR WDT instruction while the second is to use the two commands CLR WDT1 and CLR WDT2. For the first option, a simple execution of CLR WDT will clear the WDT while for the second option, both CLR WDT1 and CLR WDT2 must both be executed to successfully clear the WDT. Note that for this second option, if CLR WDT1 is used to clear the WDT, successive executions of this instruction will have no effect, only the execution of a CLR WDT2 instruction will clear the WDT. Similarly, after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer.
b7 W S2 W S1
b0 W S0 W D T S R e g is te r W D T p r e s c a le r r a te s e le c t W DTR W S0 W S1 W S2 1 :1 0 0 0 1 :2 1 0 0 1 :4 0 1 0 1 :8 1 1 0 1 :1 0 0 1 1 :3 1 0 1 1 :6 0 1 1 1 :1 1 1 1 2 4 N otused a te
6 28
Watchdog Timer Register
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C L R W D T 1 F la g C L R W D T 2 F la g 1 o r 2 In s tr u c tio n s fS
YS
C le a r W D T T y p e C o n fig u r a tio n O p tio n CLR W D T C lo c k S o u r c e C o n fig u r a tio n O p tio n 8 - b it C o u n te r ( 2 5 6 )
/4
CLR 7 - b it P r e s c a le r
W D T O s c illa to r W D T C lo c k S o u r c e
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
Voice Output
Voice Control The voice control register controls the voice ROM circuit and the DAC circuit and selects the Voice ROM latch counter. If the DAC circuit is not enabled, any DAH/DAL outputs will be invalid. Writing a 1 to the DAC bit will enable the DAC circuit, while writing a 0 to the DAC bit will disable the DAC circuit. If the voice ROM circuit is not enabled, then voice ROM data cannot be accessed. Writing a 1 to the VROMC bit will enable the voice ROM circuit, while writing a 0 to the VROMC bit will disable the voice ROM circuit. The LATCH bit determines which voice ROM address latch counter will be used as the voice ROM address latch counter. Audio Output and Volume Control - DAL, DAH, VOL The audio output is 12-bits wide whose highest 8-bits are written into the DAH register and whose lowest four bits are written into the highest four bits of the DAL register. Bits 0~3 of the DAL register are always read as zero.
b7 FAST P0AEM P0AEN LATCHC VROMC DAC b0 V O IC E C R e g is te r N o t im p le m e n te d , r e a d a s z e r o D A C E n a b le 1 : e n a b le 0 : d is a b le V o ic e c R O M 1 : e n a b le 0 : d is a b le E n a b le
There are 8 levels of volume which are setup using the VOL register. Only the highest 3-bits of this register are used for volume control, the other bits are not used and read as zero.
b7 D3 D2 D1 D0 b0 D A L R e g is te r N o t u s e d , re a d a s "0 " A u d io o u tp u t
D ig ita l to A n a lo g D a ta L o w
b7 D11 D10 D9 D8 D7 D6 D5 b0 D4
R e g is te r
D A H R e g is te r A u d io o u tp u t
D ig ita l to A n a lo g D a ta H ig h R e g is te r
b7
VO L2VO L1VO L0
b0 V O L R e g is te r N o t u s e d , re a d a s "0 " D A v o lu m e c o n tr o l d a ta
V o lu m e C o n tr o l R e g is te r
N o t im p le m e n te d , r e a d a s z e r o V o ic e R O M C o u n te r S e le c t 1 : A d d re s s L a tc h 1 0 : A d d re s s L a tc h 0 P o w e r A m p lifie r E n a b le 1 : e n a b le 0 : d is a b le P o w e r A m p lifie r M u te E n a b le 1 : e n a b le 0 : d is a b le S p e e d - U p 3 2 k H z C r y s ta l E n a b le 1 : e n a b le 0 : d is a b le
VOICE Control Register
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Voice ROM Data Address Latch Counter The Voice ROM address is 21-bits wide and therefore requires three registers to store the address. There are two sets of three registers to store this address, which are LATCH0H/LATCH0M/LATCH0L and LATCH1H/ LATCH1M/LATCH1L. The 21-bit address stored in one set of these three registers is used to access the 8-bit voice code data in the Voice ROM. After the 8-bit Voice ROM data is addressed, a few instruction cycles, of at least 4us duration, are needed to latch the Voice ROM data. After this the microcontroller can read the voice data from the LATCHD register. Example: Read an 8-bit voice ROM data which is located at address 000007H by address latch 0 Set [26H].2 ; Enable voice ROM circuit mov A, 07H ; mov LATCH0L, A ; Set LATCH0L to 07H mov A, 00H ; mov LATCH0M, A ; Set LATCH0M to 00H mov A, 00H ; mov LATCH0H, A ; Set LATCH0H to 00H call Delay ; Delay a short period of time mov A, LATCHD ; Get voice data at 000007H
Power Amplifier
Each device contains an audio power amplifier which is an integrated class AB monophonic type speaker driver. It has the properties of high S/N ratio, high slew rate, low distortion, large output voltage swing, excellent power supply ripple rejection, low power consumption, low standby current and power off control etc.
SPK SP+ SP0 .1 m F R AMP1 AMP2 A u d In C1 V
B IA S
Aud In: Audio input VBIAS: Speaker non-inverting input voltage reference SP+:Audio Positive output SP-: Audio Negative output OUTP Rising Time (tR) When AMP_EN enables the Power Amplifer, note that it requires a certain time before it can output fully on the OUTP pin. However, this delay time depends on the value of C1. The C1 capacitor is connected between VBIAS and VSS.
10R R
R B IA S AM P_EN
AM P_EN
OUTP
tR
Capacitor tR Voltage 2.2V 3V 4 15ms 15ms 15ms 30ms 30ms 30ms 90ms 90ms 90ms 185ms 185ms 185ms 0.1mF 1mF 4.7mF 10mF
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For battery based applications, power consumption is a key issue, therefore the amplifier should be turned off when in the standby state. In order to eliminate any speaker sound bursts while turning the amplifier on, the application circuit, which will incorporate a capacitance value of C1, should be adjusted in accordance with the speaker s audio frequency response. A greater value of C1 will improve the noise burst while turning on the amplifier. The recommended operation sequence is: Turn On: audio signal standby (1/2VDD) (R) enable amplifier (R) wait tR for amplifier ready (R) audio output Turn Off: audio signal finished (R) disable amplifier (R) wait tR for amplifier off (R) audio signal off If the application is not powered by batteries and there is no problem with amplifier On/Off issues, a capacitor value of 0.1mF for C1 is recommended.
SP+/ SP-
t R AM P_EN
t R
Analog to Digital Converter
The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The devices contain a 4-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. The following diagram shows the overall internal structure of the A/D converter, together with its associated registers. A/D Converter Data Registers - ADRL, ADRH The devices have a 12-bit A/D converter, two registers are required, a high byte register, known as ADRH , and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitized conversion value. They use two A/D Converter Data Registers, note that only the high byte register ADRH utilises its full 8-bit contents. The low byte register ADRL utilises only 4 of its 8-bit contents as it contains only the lower 4 bit of the 12-bit converted value.
C lo c k D iv id e R a tio ADC fO S o u rc e
SC
2 ~ 32 V
DD
ACSR A /D
R e g is te r
PC0 PC1 PC2 PC3
/A N /A N /A N /A N 1 2 3
0 ADC
r e fe r e n c e v o lta g e ADRL ADRH A /D D a ta R e g is te r s
PC R0~PC R2 P in C o n fig u r a tio n B its
AC S0~ACS1 C h a n n e l S e le c t B its
START
EOC
ADCR R e g is te r
S ta rt a n d E n d o f C o n v e r s io n B its
A/D Converter Structure
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In the following table, D0~D11 are the A/D conversion data result bits. Register ADRL ADRH Bit 7 D3 Bit 6 D2 Bit 5 D1 Bit 4 D0 D8 Bit 3 3/4 D7 Bit 2 3/4 D6 Bit 1 3/4 D5 Bit 0 3/4 D4 digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOC bit in the ADCR register will be set high and the analog to digital converter will be reset. It is the START bit that is used to control the overall on/off operation of the internal analog to digital converter. The EOC bit in the ADCR register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically cleared to zero by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOC bit in the ADCR register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. A/D Converter Clock Source Register - ACSR The clock source for the A/D converter, which originates from the system clock fOSC, is first divided by a division ratio, the value of which is determined by the ADCS1 and ADCS0 bits in the ACSR register. Although the A/D clock source is determined by the system clock fOSC, and by bits ADCS1 and ADCS0, there are some limitations on the maximum A/D clock source speed that can be selected. Refer to the following table. ACS1 0 0 1 1 ACS0 0 1 0 1 Analog Channel AN0 AN1 AN2 AN3
D11 D10 D9
A/D Data Register A/D Converter Control Register - ADCR To control the function and operation of the A/D converter, a control register known as ADCR is provided. This 8-bit register defines functions such as the selection of which analog channel is connected to the internal A/D converter, which pins are used as analog inputs and which are used as normal I/Os as well as controlling the start function and monitoring the A/D converter end of conversion status. One section of this register contains the bits ACS1~ACS0 which define the channel number. As each of the devices contains only one actual analog to digital converter circuit, each of the individual 4 analog inputs must be routed to the converter. It is the function of the ACS1~ACS0 bits in the ADCR register to determine which analog channel is actually connected to the internal A/D converter. The ADCR control register also contains the PCR2~PCR0 bits which determine which pins on Port C are used as analog inputs for the A/D converter and which pins are to be used as normal I/O pins. Note that if the PCR2~PCR0 bits are all set to zero, then all the Port C pins will be setup as normal I/Os and the internal A/D converter circuitry will be powered off to reduce the power consumption. The START bit in the ADCR register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to
ACS Table: A/D Channel Select Table
b7 START EO CB
PCR2
PCR1
PCR0
ACS1
b0 ACS0
ADCR
R e g is te r
S e le c t A /D c h a n n e l T h e d e ta il r e fe r e n c e A C S ta b le N o t im p le m e n te d r e a d a s " 0 " P o r t C A /D c h a n n e l c o n fig u r a tio n s T h e d e ta il r e fe r e n c e P C R ta b le E n d o f A /D c o n v e r s io n fla g 1 : n o t e n d o f A /D c o n v e r s io n - A /D c o n v e r s io n w a itin g o r in p r o g r e s s 0 : e n d o f A /D c o n v e r s io n - A /D c o n v e r s io n e n d e d S ta r t th e A /D c o n v e r s io n 0 (R) 1 (R) 0 : S ta rt 0 (R) 1 : R e s e t A /D c o n v e rte r a n d s e t E O C B to "1 "
ADCR Register
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b7 TEST b0 ADCS1ADCS0 ACSR R e g is te r c k s o u rc e
C C C
S e le c t A /D c o n v e r te r c lo ADCS0 ADCS1 : fO S 0 0 : fO S 1 0 0 1 : fO S 1 1 :No
/2 /8
/3 2 t im p le m e n te d
N o t im p le m e n te d , r e a d a s " 0 " F o r te s t m o d e u s e o n ly
ACSR Register
PCR2 0 0 0 0 1
PCR1 0 0 1 1 0
PCR0 0 1 0 1 0
3 PC3 PC3 PC3 PC3 AN3
2 PC2 PC2 PC2 AN2 AN2
1 PC1 PC1 AN1 AN1 AN1
0 PC0 AN0 AN0 AN0 AN0
PCR Table: Port A/D Channel Configuration Table A/D Clock Period (tAD) fOSC ADCS1, ADCS0=01 (fOSC/2) 500ns 333ns 250ns ADCS1, ADCS0=10 (fOSC/8) 2ms 1.3ms 1ms A/D Clock Period Examples ADCS1, ADCS0=00 (fOSC/32) 8ms 5.3ms 4ms ADCS1, ADCS0=11 3/4 3/4 3/4
4MHz 6MHz 8MHz
A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port C. Bits PCR2~PCR0 in the ACSR registers, not configuration options, determine whether the input pins are setup as normal Port C input/output pins or whether they are setup as analog inputs. In this way, pins can be changed under program control to change their function from normal I/O operation to analog inputs and vice versa. Pull-high resistors, which are setup through configuration options, apply to the input pins only when they are used as normal I/O pins, if setup as A/D inputs the pull-high resistors will be automatically disconnected. Note that it is not necessary to first setup the A/D pin as an input in the PBC port control register to enable the A/D input, when the PCR2~PCR0 bits enable an A/D input, the status of the port control register will be overridden. The VDD power supply pin is used as the A/D converter reference voltage, and as such analog inputs must not be allowed to exceed this value. Appropriate measures should also be taken to ensure that the VDD pin remains as stable and noise free as possible.
Initialising the A/D Converter The internal A/D converter must be initialised in a special way. Each time the Port C A/D channel selection bits are modified by the program, the A/D converter must be re-initialised. If the A/D converter is not initialized after the channel selection bits are changed, the EOCB flag may have an undefined value, which may produce a false end of conversion signal. To initialize the A/D converter after the channel selection bits have changed, then, within a time frame of one to ten instruction cycles, the START bit in the ADCR register must first be set high and then immediately cleared to zero. This will ensure that the EOCB flag is correctly set to a high condition. Summary of A/D Conversion Steps The following summarizes the individual steps that should be executed in order to implement an A/D conversion process.
* Step 1
Select the required A/D conversion clock by correctly programming bits ADCS1 and ADCS0 in the ACSR register.
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* Step 2 * Step 5
Select which channel is to be connected to the internal A/D converter by correctly programming the ACS1~ACS0 bits which are also contained in the ADCR register.
* Step 3
Select which pins on Port C are to be used as A/D inputs and configure them as A/D input pins by correctly programming the PCR2~PCR0 bits in the ADCR register. Note that this step can be combined with Step 2 into ADCR registers programming operation.
* Step 4
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. The following timing diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing.
The analog to digital conversion process can now be initialised by setting the START bit in the ADCR register from 0 to 1 and then to 0 again. Note that this bit should have been originally set to 0.
S T A R T b it s e t h ig h w ith in o n e to te n in s tr u c tio n c y c le s a fte r th e P C R 0 ~ P C R 2 b its c h a n g e s ta te START
EOCB PC R2~ PCR0
A /D s a m p lin g tim e 3 2 tA D 000B 011B
A /D s a m p lin g tim e 3 2 tA D
A /D s a m p lin g tim e 3 2 tA D 100B 000B 1 . P C p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n
AC S1~ ACS0
000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P C c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D
010B S ta rt o f A /D c o n v e r s io n
000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
D o n 't c a r e
E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e
tA D C c o n v e r s io n tim e
A /D
tA D C c o n v e r s io n tim e
A /D
A/D Conversion Timing
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SPI Serial Interface
The device includes a single SPI Serial Interfaces. The SPI interface is a full duplex serial data link, originally designed by Motorola, which allows multiple devices connected to the same SPI bus to communicate with each other. The devices communicate using a master/slave technique where only the single master device can initiate a data transfer. A simple four line signal bus is used for all communication. The four SPI lines are shared with I/O pins PD0~PD3, the function of which is chosen using a configuration option. SPI Interface Communication Four lines are used for SPI communication known as SDI - Serial Data Input, SDO - Serial Data Output, SCK Serial Clock and SCS - Slave Select. Note that the condition of the Slave Select line is conditioned by the CSEN bit in the SBCR control register. If the CSEN bit is high then the SCS line is active while if the bit is low then the SCS line will be in a floating condition. The following timing diagram depicts the basic timing protocol of the SPI bus.
SCS
SCK
SDI
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SDO
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D7 SBCR D EFAU LT SBDR D EFAU LT U CKS 0 D7
D6 M1 1 D6 U
D5 M0 1 D5 U
D4 SBEN 0 D4 U
D3 M LS 0 D3 U
D2 CSEN 0 D2 U
D1 W COL 0 D1 U
D0 TRF 0 D0 U SBCR : S E R IA L B U S
C O N T R O L R E G IS T E R SBDR : S E R IA L B U S
D A T A R E G IS T E R
N o te : "U " m e a n s u n c h a n g e d .
D a ta B u s SBDR ( R e c e iv e d D a ta R e g is te r )
D7D6D5D4D3D2D1D0 M
U X
SDO
B u ffe r SBEN
SDO
M LS M U X M U X C0C1C2 In te r n a l B a u d R a te C lo c k SCK EN a n d , s ta rt C lo c k P o la r ity a n d , s ta rt SDI
TRF AND W C O L F la g
M a s te r o r S la v e SBEN In te r n a l B u s y F la g SBEN
W r ite S B D R E n a b le /D is a b le
a n d , s ta rt EN
W r ite S B D R W r ite S B D R
SCS
M a s te r o r S la v e SBEN CSEN
SPI Block Diagram
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SPI Registers There are two registers associated with the SPI Interface. These are the SBCR register which is the control register and the SBDR which is the data register. The SBCR register is used to setup the required setup parameters for the SPI bus and also used to store associated operating flags, while the SBDR register is used for data storage. After Power on, the contents of the SBDR register will be in an unknown condition while the SBCR register will default to the condition below: CKS M1 M0 SBEN MLS CSEN WCOL TRF 0 1 1 0 0 0 0 0 SPI Bus Enable/Disable To enable the SPI bus and CSEN=1, the SCK, SDI, SDO and SCS lines should all be zero, then wait for data to be written to the SBDR (TXRX bufffer) register. For the Master Mode, after data has been written to the SBDR (TXRX buffer) register then transmission or reception will start automatically. When all the data has been transferred the TRF bit should be set. For the Slave Mode, when clock pulses are received on SCK, data in the TXRX buffer will be shifted out or data on SDI will be shifted in. To Disable the SPI bus SCK, SDI, SDO, SCS floating. SPI Operation All communication is carried out using the 4-line interface for both Master or Slave Mode. The timing diagram shows the basic operation of the bus.
Note that data written to the SBDR register will only be written to the TXRX buffer, whereas data read from the SBDR register will actual be read from the register.
b7 CKS M1 M0 SBEN M LS b0
CSENW COL TRF
SBCR
R e g is te r
T r a n s m itt/R e c e iv e F la g 0 : N o t c o m p le te 1 : T r a n s m is s io n /r e c e p tio n c o m p le te W r ite C o llis io n B it 0 : C o llis io n fr e e 1 : C o llis io n d e te c te d S e le c tio n S ig n a l E n a b le /D is a b le B it 0 : S C S flo a tin g 1 : E n a b le M S B /L S B F ir s t B it 0 : L S B s h ift fir s t 1 : M S B s h ift fir s t S e r ia l B 0 : D is a b 1:Enab D epe u s E n a b le /D is a b le B it le le n d e n t u p o n C S E N b it v e /B a u d R a te B its M as M as M as S la v te r, te r, te r, em b a u d ra te : fS b a u d ra te : fS b a u d ra te : fS ode
IO IO IO
M a s te r /S la M1 M0 0 0 0 1 1 0 1 1
/4
/1 6
C lo c k S o u r c e S e le c t B it 0 : f S IO = f S Y S / 4 1 : f S IO = f S Y S
SPI Interface Control Register
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R ( if p u ll- h ig h e d ) SCS
SCK SDI SDO SCK D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S B E N = C S E N = 1 a n d w r ite d a ta to S B D R
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The CSEN bit in the SBCR register controls the overall function of the SPI interface. Setting this bit high, will enable the SPI interface by allowing the SCS line to be active, which can then be used to control the SPI interface. If the CSEN bit is low, the SPI interface will be disabled and the SCS line will be in a floating condition and can therefore not be used for control of the SPI interface. The SBEN bit in the SBCR register must also be high which will place the SDI line in a floating condition and the SDO line high. If in Master Mode the SCK line will be either high or low depending upon the clock polarity configuration option. If in Slave Mode the SCK line will be in a floating condition. If SBEN is low then the bus will be disabled and SCS, SDI, SDO and SCK will all be in a floating condition. In the Master Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written to the SBDR register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission or reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode:
* Master Mode
Step 2. Setup the M0 and M1 bits to 00 to select the Slave Mode. The CKS bit is dont care. Step 3. Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this must be same as the Master device. Step 4. Setup the SBEN bit in the SBCR control register to enable the SPI interface. Step 5. For write operations: write data to the SBCR register, which will actually place the data into the TXRX register, then wait for the master clock and SCS signal. After this goto step 6. For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SBDR register. Step 6. Check the WCOL bit, if set high then a collision error has occurred so return to step5. If equal to zero then go to the following step. Step 7. Check the TRF bit or wait for an SBI serial bus. Step 8. Read data from the SBDR register. Step 9. Clear TRF Step10. Goto step 5 SPI Configuration Options Several configuration options exist for the SPI Interface function which must be setup during device programming. The first is a configuration to select the PD0~PD3 pins to be used as the SPI interface pins. Another option is to enable the operation of the WCOL, write collision bit, in the SBCR register. Another option exists to select the clock polarity of the SCK line. A configuration option also exists to disable or enable the operation of the CSEN bit in the SBCR register. If the configuration option disables the CSEN bit then this bit cannot be used to affect overall control of the SPI Interface. Error Detection The WCOL bit in the SBCR register is provided to indicate errors during data transfer. The bit is set by the Serial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SBDR register takes place during a data transfer operation and will prevent the write operation from continuing. The bit will be set high by the Serial Interface but has to be cleared by the user application program. The overall function of the WCOL bit can be disabled or enabled by a configuration option. Programming Considerations When the device is placed into the Power Down Mode note that data reception and transmission will continue. The TRF bit is used to generate an interrupt when the data has been transferred or received.
Step 1. Select the clock source using the CKS bit in the SBCR control register Step 2. Setup the M0 and M1 bits in the SBCR control register to select the Master Mode and the required Baud rate. Values of 00, 01 or 10 can be selected. Step 3. Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this must be same as the Slave device. Step 4. Setup the SBEN bit in the SBCR control register to enable the SPI interface. Step 5. For write operations: write the data to the SBDR register, which will actually place the data into the TXRX buffer. Then use the SCK and SCS lines to output the data. Goto to step6.For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SBDR register. Step 6. Check the WCOL bit, if set high then a collision error has occurred so return to step5. If equal to zero then go to the following step. Step 7. Check the TRF bit or wait for an SBI serial bus. Step 8. Read data from the SBDR register. Step 9. Clear TRF. Step10. Goto step 5.
* Slave Mode
Step 1. The CKS bit has a dont care value in the slave mode.
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Low Voltage Detect Function
A low voltage detect function is implemented within the microcontroller. The LVD function is controlled using the LVDC register and configuration options. To enable the LVD function, both the LVD configuration option should be enabled and the LVEN bit should be set high. After setting the LVEN bit high, the circuit requires about 100ms to stabilise. After this time has elapsed, the LVFG bit can be monitored to look for low voltage conditions.
LVEN B it LVD O n /O ff
L V D E n a b le C o n fig u r a tio n O p tio n L V S 0 /L V S 1 B it L V D V o lta g e L e v e l C o fig u r a tio n O p tio n MUX
LVD F u n c tio n LVD V o lta g e L e v e l
LVFG
L V D V o lta g e L e v e l S o u r c e S e le c t
LVD Block Diagram The LVS0 and LVS1 bits are used to define the LVD voltage threshold level, however configuration options can also be used to define this voltage. A configuration option is used to decide whether these two register bits or the configuration option is used to define the LVD voltage threshold level. As the low voltage detector circuitry will consume a certain amount of power, the LVEN bit can be reset to zero to turn off the LVD internal circuitry to reduce power consumption.
b7 LVFG LVEN
LVS1
b0 LVS0
LVDC
R e g is te r V o lta g e .2 V .3 V .4 V .5 V
L V D v o lta g e s e le c t LVD LVS0 LVS1 2 0 0 2 1 0 2 0 1 2 1 1
N o t im p le m e n te d , r e a d a s " 0 " L o w V o lta g e D e te c t E n a b le 1 : e n a b le 0 : d is a b le L o w V o lta g e D e te c t L e v e l 1 : L B IN p in v o lta g e is le s s th a n 0 : L B IN v o lta g e is n o t le s s th a n N o t im p le m e n te d , r e a s a s " 0 "
Low Voltage Detect Control Register - LVDC
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Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software. No. I/O Options 1 2 3 4 5 6 7 PA0~PA7: wake-up enable or disable (bit option) PA0~PA7: pull-high enable or disable (bit option) PB0~PB7: pull-high enable or disable (bit option) PC0~PC7: pull-high enable or disable (bit option) PD0~PD7: pull-high enable or disable (bit option) PE0~PE7: pull-high enable or disable (bit option) PD pin shared function select: select PD3~PD0 as I/O pins or as serial interface function Options
Oscillation Option 8 9 OSC type selection: RC or crystal RTC: enable or disable
Interrupt Option 10 INT Triggering edge: Falling or both
Watchdog Options 11 12 13 WDT: enable or disable WDT clock source: WDROSC or T1 CLRWDT instructions: 1 or 2 instructions
Low Voltage Reset Option 14 LVR select: enable or disable
Low Voltage Detect Option 15 16 17 LVD voltage: 2.2V~2.5V LVD select: enable or disable LVD voltage level control select: Register bits or configuration option
Serial interface Option 18 19 20 Serial interface CPOL: falling edge or rising edge Serial interface WCOL: enable or disable Serial interface CSEN: enable or disable
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Application Circuits
V 10W
DD
0 .1 m F
47mF
VDDM
VDDA1
VDDA
OSC2 OSC1
V
DD
VDD 100mF 100kW RES 0 .1 m F
PA0~PA7 PB0~PB7 PC0~PC 7 PD0~PD 7 PE0~PE7 0 .1 m F
R
OSC
V
DD
A U D _ IN
AU D_O UT
IN T VSS VSSA VSSA1 VSSM
50kW V B IA S 10mF SP+ SPSPK
H T 8 6 A 3 6 /H T 8 6 A 7 2 /H T 8 6 A R 7 2
V 10W
DD
0 .1 m F
47mF
VDDM
VDDA1
VDDA
OSC2 OSC1
V
DD
4M H z~ 8M H z
VDD 100mF 100kW RES 0 .1 m F
PA0~PA7 PB0~PB7 PC0~PC 7 PD0~PD 7 PE0~PE7 0 .1 m F
V
DD
A U D _ IN AU D_O UT IN T VSS VSSA VSSA1 VSSM 50kW V B IA S 10mF SP+ SPSPK
H T 8 6 A 3 6 /H T 8 6 A 7 2 /H T 8 6 A R 7 2
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Instruction Set
Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
Cycles 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Flag Affected Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
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Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.00 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 56 March 19, 2010
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CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
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CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
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INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
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OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
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RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
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SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
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SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
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SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
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Package Information
44-pin QFP (10mm10mm) Outline Dimensions
C D G 23 I 34 22 L F A B E 44 12 K 1 11 a J 33 H
Symbol A B C D E F G H I J K L a
Dimensions in mm Min. 13 9.9 13 9.9 3/4 3/4 1.9 3/4 0.25 0.73 0.1 3/4 0 Nom. 3/4 3/4 3/4 3/4 0.8 0.3 3/4 3/4 3/4 3/4 3/4 0.1 3/4 Max. 13.4 10.1 13.4 10.1 3/4 3/4 2.2 2.7 0.5 0.93 0.2 3/4 7
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64-pin LQFP (10mm10mm) Outline Dimensions
C D 48 33 G H
I 49 32 F
A B
E
64
17 K 1 16 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 11.9 9.9 11.9 9.9 3/4 3/4 1.35 3/4 3/4 0.45 0.1 0 Nom. 3/4 3/4 3/4 3/4 0.5 0.2 3/4 3/4 0.1 3/4 3/4 3/4 Max. 12.1 10.1 12.1 10.1 3/4 3/4 1.45 1.6 3/4 0.75 0.2 7
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2010 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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